1. Field of the Invention
The present invention relates to a control signal training system in an integrated circuit, to a memory module and a computer system. The invention further relates to a control signal training method.
2. Description of the Related Art
Demands imposed on large scale integrated circuits are constantly increasing. In the case of memory devices, said demands mainly translate into speed and storage capacity. As far as high-speed memory devices are concerned, the computer industry has established the so-called DRAM (Dynamic Random Access Memory) as an economic means for high speed and high capacity data storage.
Although a DRAM requires continuous refreshing of stored information, speed and information density, combined with relatively low cost, have put DRAM in a pivotal position in the field of information technology. Almost every modern computer system, ranging, for example, from PDAs over notebook computers and desktop personal computers to high-end servers, takes advantage of this economic and fast data-storage technology.
While the storage capacity of modern memory devices are steadily increasing, the memory device must provide means for a fast and efficient access to the information held in the device. For synchronisation to other components of a computing system or a memory module, data is read from or written into a conventional memory device with respect to a so-called clock signal. This clock signal may periodically alternate between a low-level and a high-level, in this way defining a time unit of the system.
In order to increase data throughput, conventional memory devices employ the so-called double data rate (DDR) concept for data exchange. In this concept, two words of data are exchanged per cycle: a first word is transmitted upon the transition of the clock signal from the low-level to the high-level, and a second word is transmitted upon the subsequent transition of the clock signal from the high-level to the low-level. With this concept, data throughput is increased by a factor of two in respect to the so-called single data rate (SDR) memory devices. The latter SDR-devices only exchange one word of data per clock cycle, for example, upon one transition, either the high-level to low-level transition or the low-level to high-level transition.
Since data exchange rate in modern electronic memory modules is very high, not only the transmission bus-width has increased over recent years, but also the clock frequency of the clock signal has already reached the gigahertz domain. Since in DDR memory devices, the data changes twice within a period of the clock signal, precise timing may be important to avoid data-scrambling and/or data loss. Modern memory modules, therefore, may employ carefully designed signal traces amongst components to ensure correct timing and synchronization, i.e. correct times of arrival of the signals in relation to each other at respective positions, such as landing pads (e.g., pins) for interconnection of the components of the memory module.
Since these timing requirements may result in a complex routing of the manifold of signal traces, the routing itself may represent a sophisticated task and may also limit the density of components that may be placed on a printed circuit board. Conventional high performance memory modules may therefore employ memory controllers which, for example, upon initialization determine an optimized timing between a data signal line and a clock signal to allow for a correct time of arrival of the data signal at the memory device in relation to the clock signal. During a training stage, such a memory controller may write certain data to and read certain data from a memory device, for example a DRAM, and shift the data signal in respect to the clock signal within the time domain, such that the data signal arrives at the memory device with a well-defined synchronisation to the clock signal. The memory controller may vary this time shift until a written value corresponds to a read value, which indicates that timing is correct. In this way, a reliable, fast, and efficient exchange of information is enabled. Since this training sequence may require bi-directional data exchange, certain components or registers are not available for such training methods, since the provision of bi-directionality may require a disadvantageous addition of circuitry. Additional circuitry may not only increase device complexity and cost, but may also worsen signal transmission characteristics, and, therefore, the reliability.